1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to delay locked loops (DLLs).
2. Description of the Related Art
Delay-locked loops (DLLs) are commonly used circuits in computers and other digital systems. DLLs may be used to provide an arbitrary delay that is compensated for process, voltage, and temperature (PVT) variations.
FIG. 1 illustrates one embodiment of a typical DLL. The DLL includes a phase detector coupled to receive a reference clock and configured to make a phase comparison between the reference clock and a feedback signal. The output of the phase detector is received by a digital filter which then filters the digital signal and conveys it to an up/down counter. The filtered signal received by the up/down counter represents a phase relationship between the reference clock signal and the feedback signal (wherein the goal of the feedback loop is to align the falling edge of the feedback clock with the rising edge of the reference clock), and thus may cause the up/down counter to count either up or down in order to obtain the desired phase relationship. The output of the up/down counter may be provided to a digital-to-analog converter (DAC), which is configured to generate and provide a control voltage based on the count provided by the counter. The control voltage is received by a voltage controlled delay line (VCDL) which is then configured to provide the desired delay indicated by the control voltage. The delay output is then provided through a multiplexer and a phase interpolator (PI) to a clock tree, from which a clock signal is conveyed. A second multiplexer/PI conveys the feedback signal to the phase detector.
The output provided by the VCDL to each multiplexer/PI is a delayed signal passed through one of several lines (representing outputs of delay elements in the VCDL) through the multiplexer (which selects the proper output) and the PI, which interpolates between two phase divisions. Thus, if the VCDL has 16 outputs (and thus the multiplexer is a 16:1 multiplexer) and the PI can interpolate between two phase divisions, the clock cycle of the reference clock can be divided up in to 32 equal parts.
While the embodiment shown in FIG. 1 may be acceptable in some circumstances, it may introduce a significant static error into the feedback signal (and throughout the DLL) between the phases of the clock signal. Furthermore, since the embodiment utilizes a separate multiplexer/PI for the feedback path and the output clock signal, mismatches between these two units may be unaccounted for. The static error and mismatches may be unacceptable for many applications, particularly in the light of increasing clock speeds in computers and other digital systems.